Analog Devices Advantiv ADV7611 Hardware User's Manual page 125

Hardware User Guide
LLC
PIXEL BUS Cr Y FF 00
ACTIVE VIDEO
HS OUTPUT
START_HS[9:0]
B
C
START_HS[9:0] , Addr 44 (CP), Address 0x7C[3:2]; Address 0x7E[7:0]
A control to shift the position of the leading edge of the HSync output by the CP core.
This register stores a signed value in a twos complement format. START_HS[9:0] is the number of pixel clocks by which the leading edge
of the HSync is shifted (for example, 0x3FF corresponds to a shift of one pixel clock away from the active video, 0x005 corresponds to a
shift of five pixel clocks toward the active video).
Function
START_HS[9:0]
0x000 (default)
0x000 to 0x1FF
0x200 to 0x3FF
Table 52. Controlling the Beginning of the HS Timing Signal
START_HS[9:0]
0000000000 (default)
0000000001
0100000000
0111111111
1111111111
1011111111
1000000000
1 HS START closer to active video.
2
HS START away from active video.
00 XY 80 10 80 10
EAV
D
END_HS[9:0]
4 LLC1
Description
Default value.
The leading edge of the HSync is shifted toward the active video.
The leading edge of the HSync is shifted away from the active video.
Hex Result
0x000 No move
0x001
1
1 × sec shift later than default
LLC
0x100
1
256 ×
LLC
0x1FF
1
511 ×
LLC
0x3FF
1
1 × sec shift earlier than default
LLC
0x3FE
1
256 ×
LLC
0x200
1
512 ×
LLC
80 10 ....... ....... FF 00
H BLANK SAV
A
C
Figure 49. HS Timing
1
sec shift later than default
sec shift later than default
2
sec shift earlier than default
sec shift earlier than default
Rev. A | Page 125 of 184
00 XY Cb Y Cr Y Cb
ACTIVE VIDEO
B
Note
Default
Minimum →
Maximum →
Minimum ←
Maximum ←
UG-180
Y Cr .......