Analog Devices Advantiv ADV7611 Hardware User's Manual page 36

UG-180
NEW_TMDS_FRQ_RAW , IO, Address 0x83[1] (Read Only)
Status of new TMDS frequency interrupt signal. When set to 1, it indicates the TMDS Frequency has changed by more than the tolerance
set in FREQTOLERANCE[3:0]. Once set, this bit will remain high until it is cleared via NEW_TMDS_FREQ_CLR.
Function
NEW_TMDS_FRQ_RAW
0 (default)
1
FREQTOLERANCE[3:0] , Addr 68 (HDMI), Address 0x0D[3:0]
Sets the tolerance in MHz for new TMDS frequency detection. This tolerance is used for the audio mute mask MT_MSK_VCLK_CHNG
and the HDMI status bit NEW_TMDS_FRQ_RAW.
Function
FREQTOLERANCE[3:0]
0100 (default)
xxxx
DEEP COLOR MODE SUPPORT
The Deep Color mode information that the ADV7611 extracts from the general control packet can be read back from
DEEP_COLOR_MODE[1:0].
DEEP_COLOR_MODE[1:0] , Addr 68 (HDMI), Address 0x0B[7:6] (Read Only)
A readback of the Deep Color mode information extracted from the general control packet
Function
DEEP_COLOR_MODE[1:0]
00 (default)
01
10
Notes
•
Deep Color mode can be monitored via DEEP_COLOR_CHNG_RAW, which indicates if the color depth of the processed HDMI
stream has changed.
•
The ADV7611 can be configured to trigger an interrupt when the DEEP_COLOR_CHNG_RAW bit changes from 0 to 1. In that
configuration, the interrupt status DEEP_COLOR_CHNG_ST indicates that DEEP_COLOR_CHNG_RAW has changed from 0 to 1.
Refer to the Interrupts section for additional information on the configuration of interrupts.
DEEP_COLOR_CHNG_RAW , IO, Address 0x83[7] (Read Only)
Status of Deep Color mode changed interrupt signal. When set to 1 it indicates a change in the deep color mode has been detected. Once
set, this bit will remain high until it is cleared via DEEP_COLOR_CHNG_CLR.
Function
DEEP_COLOR_CHNG_RAW
0 (default)
1
VIDEO FIFO
The ADV7611 contains a FIFO located between the incoming TMDS data and the CP core (refer to Figure 5). Data arriving over the
HDMI link will be at 1X for non-Deep Color mode (8 bits per channel), and 1.25X, 1.5X, or 2X for deep color modes (30, 36, and 48 bits,
respectively). Data unpacking and data rate reduction must be performed on the incoming HDMI data to provide the CP core with the
correct data rate and data bit width. The video FIFO is used to pass data safely across the clock domains.
The video FIFO also provides extreme robustness to jitter on the TMDS clock. The CP clock is generated by a DPLL running on the
incoming TMDS clock, and the CP clock may contain less jitter than the incoming TMDS clock. The video FIFO provides immunity to
the incoming jitter and the resultant clock phase mismatch between the CP clock and the TMDS clock.
Description
TMDS frequency has not changed by more than tolerance set in FREQTOLERANCE[3:0] in the HDMI map.
TMDS frequency has changed by more than tolerance set in FREQTOLERANCE[3:0] in the HDMI map.
Description
Default tolerance in MHz for new TMDS frequency detection
Tolerance in MHz for new TMDS frequency detection
Description
8-bits per channel
10-bits per channel
12-bits per channel
Description
Deep color mode has not changed
Change in deep color triggered this interrupt
Rev. A | Page 36 of 184
Hardware User Guide