Analog Devices Advantiv ADV7611 Hardware User's Manual page 120

UG-180
CH1_FCL[12:0] , Addr 44 (CP), Address 0xB8[4:0]; Address 0xB9[7:0] (Read Only)
A readback for the Sync Channel 1 field count length.
Number of crystal clock cycles between successive VSyncs measured by Sync Channel 1 STDI or in 1/256th of a field. The readback from
this field is valid if CH1_STDI_DVALID is high.
Function
CH1_FCL[12:0]
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CH1_STDI_INTLCD , Addr 44 (CP), Address 0xB1[6] (Read Only)
Interlaced vs. progressive mode detected by Sync Channel 1 STDI. The readback from this register is valid if CH1_STDI_DVALID is high.
Function
CH1_STDI_INTLCD
0 (default)
1
STDI Usage
Figure 45 shows a flowchart of the intended usage of the STDI block.
SET CH1_STDI_CONT TO 0
SET CH1_TRIG_STDI TO 0 ≥ 1
(POSITIVE TRANSITION ON BIT)
TO START THE STDI
STATE MACHINE
Description
Readback value
Description
Indicates a video signal on Sync Channel 1 with noninterlaced timing
Indicates a signal on Sync Channel 1 with interlaced timing
NO
CONTINUOUS
MODE?
STDI BLOCK
EXAMINES INPUT
(FLAGS THIS BY SETTING
CH1_STDI_DVALID TO 0)
LOW
READ AND
CH1_STDI_DVALID
END APPLICATION READS
VIDEO DETECTION RESULTS
CH1_BL[13:0], CH1_LCVS[4:0],
CH1_LCF[10:0], AND CH1_FCL[12:0]
END APPLICATION DETERMINES
VIDEO STANARD AND PROGRAMS
PRIM_MODE AND
VID_STD ACCORDINGLY
Figure 45. STDI Usage Flowchart
Rev. A | Page 120 of 184
YES
SET CH1_STDI_CONT TO 1
STDI STATE MACHINE
RUNS CONTINUOUSLY
HIGH
SOFTWARE FUNCTION OF SYSTEM CONTROLLER
DECODER HARDWARE FUNCTION
Hardware User Guide