Analog Devices Advantiv ADV7611 Hardware User's Manual page 126

UG-180
END_HS[9:0] , Addr 44 (CP), Address 0x7C[1:0]; Address 0x7D[7:0]
A control to shift the position of the trailing edge of the HSync output by the CP core.
This register stores a signed value in a twos complement format. HS_END[9:0] is the number of pixel clocks by which the leading edge of
the HSync is shifted (for example, 0x3FF corresponds to a shift of one pixel clock away from the active video, 0x005 corresponds to a shift
of five pixel clocks toward the active video).
Function
END_HS[9:0]
0x000 (default)
0x000 to 0x1FF
0x200 to 0x3FF
Table 53. Controlling the End of the HS Timing Signal
END_HS[9:0]
0000000000 (default)
0000000001
0100000000
0111111111
1111111111
1011111111
1000000000
1 Closer to active video.
2 Away from active video.
EIA_861_COMPLIANCE, Addr 44 (CP), Address 0x69[2]
Control for compliance to 861B for 525p.This bit set the start of the VBI for the 525p standard only.
Function
EIA_861_COMPLIANCE
0 (default)
1
VSync Timing Controls
This section describes the programming of the VS timing signals. The VS signal is shown in Figure 50, Figure 51, Figure 52, Figure 53, Figure 54,
Figure 55, and Figure 56 and can be adjusted in the described manner.
Table 54. VS Default Timing
Characteristic
START_VS range maximum
START_VS range minimum
END_VS range maximum
END_VS range minimum
START_VS[3:0] , Addr 44 (CP), Address 0x7F[7:4]
A control to shift the position of the leading edge of the VSync output by the CP core.
This register stores a signed value in a twos complement format. START_VS[3:0] is the number of lines by which the leading edge of the
VSync is shifted (for example, 0x0F corresponds to a shift by 1 line toward the active video, 0x01 corresponds to a shift of 1 line away
from the active video).
Description
Default value.
The trailing edge of the HSync is shifted toward the active video.
The trailing edge of the HSync is shifted away from the active video.
Hex Result
0x000 No move (default)
0x001
1
1 × sec shift later than default
LLC
0x100
1
256× sec shift later than default
LLC
0x1FF
1
511× sec shift later than default
LLC
0x3FF
1
1 × sec shift earlier than default
LLC
0x3FE
1
256 × sec shift earlier than default
LLC
0x200
1
512 × sec shift earlier than default
LLC
Description
The VBI region starts on Line 1.
The VBI region starts on Line 523. The start of the VBI region is compliant with the 861 specification.
Units Direction
→
Lines
←
Lines
→
Lines
←
Lines
1
2
525i 625i
7 7
8 8
7 7
8 8
Rev. A | Page 126 of 184
Hardware User Guide
Note
Minimum →
Maximum →
Minimum ←
Maximum ←
525p 625p 720p
7 7 7
8 8 8
7 7 7
8 8 8
1080i
7
8
7
8