Analog Devices Advantiv ADV7611 Hardware User's Manual page 144

UG-180
CEC_RX_RDY0_ST , IO, Address 0x93[3] (Read Only)
Latched status of CEC_RX_RDY0_RAW signal. This bit is only valid if enabled via the corresponding INT1 or INT2 interrupt mask bit.
When a message has been received into Buffer 0, this bit is set. Once set, this bit will remain high until the interrupt is cleared via
CEC_RX_RDY0_CLR.
Function
CEC_RX_RDY0_ST
0 (default)
1
CEC_RX_RDY1_ST , IO, Address 0x93[4] (Read Only)
Latched status of CEC_RX_RDY1_RAW signal. This bit is only valid if enabled via the corresponding INT1 or INT2 interrupt mask bit.
When a message has been received into Buffer 1, this bit is set. Once set, this bit will remain high until the interrupt is cleared via
CEC_RX_RDY0_CLR.
Function
CEC_RX_RDY1_ST
0 (default)
1
CEC_RX_RDY2_ST , IO, Address 0x93[5] (Read Only)
Latched status of CEC_RX_RDY2_RAW signal. This bit is only valid if enabled via the corresponding INT1 or INT2 interrupt mask bit.
When a message has been received into Buffer 2, this bit is set. Once set, this bit will remain high until the interrupt is cleared via
CEC_RX_RDY0_CLR.
Function
CEC_RX_RDY2_ST
0 (default)
1
When a message (other than a polling message) is received it is loaded into the first available frame buffer (starting with Buffer 0) and a
2-bit time stamp is generated for that buffer. If the corresponding interrupt mask bit is set the status bit relating to that buffer is set and an
interrupt is generated to alert the host processor to the fact that a message has been received.
When all three frame buffers are full, the receive module can no longer receive CEC messages and will not acknowledge any new
messages (other than polling messages). In the case that only one frame buffer is enabled (the default condition) then only one message
can be received. In this case the received message is always available in Buffer 0.
The host can read the receive buffers (refer to Table 62, Table 63 and Table 64) to get the messages that were addressed to the CEC
receiver. The length of each received message is available in the corresponding frame length register.
Table 62. CEC Incoming Frame Buffer 0 Registers
Register Name
CEC_BUF0_RX_FRAME_HEADER[7:0]
CEC_BUF0_RX_FRAME_DATA0[7:0]
CEC_BUF0_RX_FRAME_DATA1[7:0]
CEC_BUF0_RX_FRAME_DATA2[7:0]
CEC_BUF0_RX_FRAME_DATA3[7:0]
CEC_BUF0_RX_FRAME_DATA4[7:0]
CEC_BUF0_RX_FRAME_DATA5[7:0]
CEC_BUF0_RX_FRAME_DATA6[7:0]
CEC_BUF0_RX_FRAME_DATA7[7:0]
CEC_BUF0_RX_FRAME_DATA8[7:0]
CEC_BUF0_RX_FRAME_DATA9[7:0]
CEC_BUF0_RX_FRAME_DATA10[7:0]
CEC_BUF0_RX_FRAME_DATA11[7:0]
CEC_BUF0_RX_FRAME_DATA12[7:0]
CEC_BUF0_RX_FRAME_DATA13[7:0]
CEC_BUF0_RX_FRAME_DATA14[7:0]
Description
No change
New CEC message received in Buffer 0
Description
No change
New CEC message received in Buffer 1
Description
No change
New CEC message received in Buffer 2
CEC Map Address
0x15
0x16
0x17
0x18
0x19
0x1A
0x1B
0x1C
0x1D
0x1E
0x1F
0x20
0x21
0x22
0x23
0x24
Rev. A | Page 144 of 184
Description
Header of message in Frame Buffer 0
Byte 0 of message in Frame Buffer 0
Byte 1 of message in Frame Buffer 0
Byte 2 of message in Frame Buffer 0
Byte 3 of message in Frame Buffer 0
Byte 4 of message in Frame Buffer 0
Byte 5 of message in Frame Buffer 0
Byte 6 of message in Frame Buffer 0
Byte 7 of message in Frame Buffer 0
Byte 8 of message in Frame Buffer 0
Byte 9 of message in Frame Buffer 0
Byte 10 of message in Frame Buffer 0
Byte 11 of message in Frame Buffer 0
Byte 12 of message in Frame Buffer 0
Byte 13 of message in Frame Buffer 0
Byte 14 of message in Frame Buffer 0
Hardware User Guide