Analog Devices Advantiv ADV7611 Hardware User's Manual page 168

UG-180
HDMI Edg INT Status 1 register consists of fields: NEW_ISRC2_PCKT_ST, NEW_ISRC1_PCKT_ST, NEW_ACP_PCKT_ST,
NEW_VS_INFO_ST, NEW_MS_INFO_ST, NEW_SPD_INFO_ST, and NEW_AUDIO_INFO_ST.
NEW_ISRC2_PCKT_ST , IO, Address 0x7A[7] (Read Only)
Latched status for the new ISRC2 packet interrupt. Once set, this bit will remain high until the interrupt is cleared via
NEW_ISRC2_PCKT_CLR. This bit is only valid if enabled via the corresponding INT1 or INT2 interrupt mask bit.
Function
NEW_ISRC2_PCKT_ST
0 (default)
1
NEW_ISRC1_PCKT_ST , IO, Address 0x7A[6] (Read Only)
Latched status for the new ISRC1 packet interrupt. Once set, this bit will remain high until the interrupt is cleared via
NEW_ISRC1_PCKT_CLR. This bit is only valid if enabled via the corresponding INT1 or INT2 interrupt mask bit.
Function
NEW_ISRC1_PCKT_ST
0 (default)
1
NEW_ACP_PCKT_ST , IO, Address 0x7A[5] (Read Only)
Latched status for the new ACP packet interrupt. Once set, this bit will remain high until the interrupt is cleared via
NEW_ACP_PCKT_CLR. This bit is only valid if enabled via the corresponding INT1 or INT2 interrupt mask bit.
Function
NEW_ACP_PCKT_ST
0 (default)
1
NEW_VS_INFO_ST , IO, Address 0x7A[4] (Read Only)
Latched status for the new vendor specific InfoFrame interrupt. Once set, this bit will remain high until the interrupt is cleared via
NEW_VS_INFO_CLR. This bit is only valid if enabled via the corresponding INT1 or INT2 interrupt mask bit.
Function
NEW_VS_INFO_ST
0 (default)
1
NEW_MS_INFO_ST , IO, Address 0x7A[3] (Read Only)
Latched status for the new MPEG source InfoFrame interrupt. Once set, this bit will remain high until the interrupt is cleared via
NEW_MS_INFO_CLR. This bit is only valid if enabled via the corresponding INT1 or INT2 interrupt mask bit.
Function
NEW_MS_INFO_ST
0 (default)
1
NEW_SPD_INFO_ST , IO, Address 0x7A[2] (Read Only)
Latched status for the new source product descriptor InfoFrame interrupt. Once set, this bit will remain high until the interrupt is cleared
via NEW_SPD_INFO_CLR. This bit is only valid if enabled via the corresponding INT1 or INT2 interrupt mask bit.
Function
NEW_SPD_INFO_ST
0 (default)
1
Description
No new ISRC2 packet received. An interrupt has not been generated.
ISRC2 packet with new content received. An interrupt has been generated.
Description
No new ISRC1 packet received. An interrupt has not been generated.
ISRC1 packet with new content received. An interrupt has been generated.
Description
No new ACP packet received. An interrupt has not been generated.
ACP packet with new content received. An interrupt has been generated.
Description
No new VS packet received. An interrupt has not been generated.
VS packet with new content received. An interrupt has been generated.
Description
No new MPEG Source InfoFrame received. Interrupt has not been generated.
MPEG Source InfoFrame with new content received. Interrupt has been generated.
Description
No new SPD InfoFrame received. Interrupt has not been generated.
SPD InfoFrame with new content received. Interrupt has been generated.
Rev. A | Page 168 of 184
Hardware User Guide