Analog Devices Advantiv ADV7611 Hardware User's Manual page 146

UG-180
Table 64. CEC Incoming Frame Buffer 2 Registers
Register Name
CEC_BUF2_RX_FRAME_HEADER[7:0]
CEC_BUF2_RX_FRAME_DATA0[7:0]
CEC_BUF2_RX_FRAME_DATA1[7:0]
CEC_BUF2_RX_FRAME_DATA2[7:0]
CEC_BUF2_RX_FRAME_DATA3[7:0]
CEC_BUF2_RX_FRAME_DATA4[7:0]
CEC_BUF2_RX_FRAME_DATA5[7:0]
CEC_BUF2_RX_FRAME_DATA6[7:0]
CEC_BUF2_RX_FRAME_DATA7[7:0]
CEC_BUF2_RX_FRAME_DATA8[7:0]
CEC_BUF2_RX_FRAME_DATA9[7:0]
CEC_BUF2_RX_FRAME_DATA10[7:0]
CEC_BUF2_RX_FRAME_DATA11[7:0]
CEC_BUF2_RX_FRAME_DATA12[7:0]
CEC_BUF2_RX_FRAME_DATA13[7:0]
CEC_BUF2_RX_FRAME_DATA14[7:0]
CEC_BUF2_RX_FRAME_LENGTH[4:0] , Addr 80 (CEC), Address 0x75[4:0] (Read Only)
Function
CEC_BUF2_RX_FRAME_LENGTH[4:0]
xxxxx
CEC_CLR_RX_RDY2 , Addr 80 (CEC), Address 0x2C[3] (Self-Clearing)
Clear control for CEC_RX_RDY2.
Function
CEC_CLR_RX_RDY2
0 (default)
1
CEC Message Reception Overview
This section describes how messages are received and stored when only one frame buffer is enabled (default condition).
1. Initially the receive buffer (Buffer 0) is empty.
2. A message is received and stored in receive buffer 0, and CEC_BUF0_TIMESTAMP is set to 0b01. If the corresponding interrupt
mask bit is set CEC_RX_RDY0_ST goes high and an interrupt is generated to alert the host processor that a message has been
received. No more messages can be received until the processor reads out the received message.
3. The host processor responds to the interrupt, or polls the CEC_BUF0_TIMESTAMP register and realizes a message has been
received, and reads receive buffer 0. Once the message is read the processor sets CEC_RX_RDY0_CLR which resets the buffer 0
timestamp to 0b00 and will also clear the buffer 0 status bit (if applicable). The CEC module is now ready to receive the next
incoming message.
This section describes how messages are received and stored, how the time stamps are generated, and what happens when the host reads a
received message when all three frame buffers are enabled.
1. Initially all buffers are empty and all time stamps are 0b00.
2. A message is received and stored in receive buffer 0, and CEC_BUF0_TIMESTAMP is set to 0b01. If the corresponding interrupt
mask bit is set CEC_RX_RDY0_ST goes high and an interrupt is generated to alert the host processor that a message has been
received.
3. Another message is received and stored in Receive Buffer 1, and CEC_BUF1_TIMESTAMP is set to 0b10. If the corresponding
interrupt mask bit is set CEC_RX_RDY1_ST goes high and an interrupt is generated to alert the host processor that a message has
been received.
4. The host processor responds to the interrupts, or polls the timestamps and realizes that messages have been received, and reads the
three time stamps to determine which receive buffer to read first. The buffer with the earliest time stamp should be read first, so in
this example the processor should read Receive Buffer 0 first. Once the message has been read the processor sets
CEC_RX_RDY0_CLR, which resets the Buffer 0 timestamp to 0b00 and will also clear the buffer 0 status bit (if applicable).
CEC Map Address
0x65
0x66
0x67
0x68
0x69
0x6A
0x6B
0x6C
0x6D
0x6E
0x6F
0x70
0x71
0x72
0x73
0x74
Description
The total number of bytes (including header byte) that were received into buffer 2
Description
Retain the value of the CEC_RX_RDY2 flag
Clear the value of the CEC_RX_RDY2 flag
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Description
Header of message in Frame Buffer 2
Byte 0 of message in Frame Buffer 2
Byte 1 of message in Frame Buffer 2
Byte 2 of message in Frame Buffer 2
Byte 3 of message in Frame Buffer 2
Byte 4 of message in Frame Buffer 2
Byte 5 of message in Frame Buffer 2
Byte 6 of message in Frame Buffer 2
Byte 7 of message in Frame Buffer 2
Byte 8 of message in Frame Buffer 2
Byte 9 of message in Frame Buffer 2
Byte 10 of message in Frame Buffer 2
Byte 11 of message in Frame Buffer 2
Byte 12 of message in Frame Buffer 2
Byte 13 of message in Frame Buffer 2
Byte 14 of message in Frame Buffer 2
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