Analog Devices Advantiv ADV7611 Hardware User's Manual page 103

Hardware User Guide
COMPONENT PROCESSOR
COMPONENT PROCESSING
SYNC PROCESSING
CHANNEL
VIDEO DATA
CHA, CHB, AND
CHC INPUT
INTRODUCTION TO THE COMPONENT PROCESSOR
A simplified block diagram of the the component processor (CP) on the ADV7611 is shown in Figure 34. Data is supplied to the CP from
the data preprocessor (DPP). The CP circuitry is activated under the control of
The CP is activated for the following modes of operation:
•
Manual and automatic gain control
•
Manual offset correction
•
Saturation
•
Insertion of timing codes and blanking data
The CP also has the following capabilities:
•
Generates HSync, VSync, FIELD, and data enable (DE) timing reference outputs
•
Color space conversion
•
Color control adjustment
CLAMP OPERATION
The CP contains a digital fine clamp block. Its main purposes is to allow a clamp to operate even if the input signal is coming from a
digital source
The digital fine clamp operates in three separate feedback loops, one for each channel. The incoming video signal level is measured at the
back porch. The level error, that is, clamp error, is compensated for by subtracting or adding a digital number to the data stream.
The digital clamp loop can be operated in an automatic or a manual mode with the following options:
•
The clamp values for Channel B and Channel C can be set manually. This is the recommended mode.
•
The clamp value is determined automatically on a line-by-line basis.
•
The clamp loops can be frozen. This means that the currently active offsets will no longer be updated but will be applied
permanently.
•
The clamp value for channel A can be set manually (static value).
Note: The target clamp level for black input is a digital code of 0. This is to facilitate the highest possible signal to noise ratio (SNR).
Some interfaces, for example, ITU-R. BT656, require black to correspond to a value other than 0. To facilitate this, there is an additional
independent offset adder block after the gain multipliers for which separate fixed offset values can be supplied. Refer to the CP Offset
Block section for additional information.
STANDARD
IDENTIFICATION
(STDI)
DIGITAL
GAIN
DELAY FINE
CONTROL
CLAMP
Figure 34. Component Processor Block Diagram
SYNC EXTRACTOR
OFFSET
CP CSC
ADDER
ACTIVE PEAK
AND HSYNC DEPTH
PRIM_MODE[3:0]
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HS/VS/F
OUTPUT
VIDEO DATA
CHA, CHB, AND
CHC OUTPUT
MEASUREMENT
2
BLOCK (≥I C)
AV CODE
INSERTION
VIDEO DATA
PROCESSING BLOCK
and VID_STD[5:0].
UG-180