Analog Devices Advantiv ADV7611 Hardware User's Manual page 12

UG-180
Pin No. Mnemonic Type
25 LLC Digital video output
26 P15 Digital video output
27 P14 Digital video output
28 P13 Digital video output
29 P12 Digital video output
30 P11 Digital video output
31 P10 Digital video output
32 P9 Digital video output
33 P8 Digital video output
34 DVDDIO Power
35 P7 Digital video output
36 P6 Digital video output
37 P5 Digital video output
38 P4 Digital video output
39 P3 Digital video output
40 DVDD Power
41 P2 Digital video output
42 P1 Digital video output
43 P0 Digital video output
44 DVDDIO Power
45 DE Miscellaneous digital
46 HS Digital video output
47 VS/FIELD/ALSB Digital input/output
48 AP Miscellaneous
49 SCLK/INT2 Miscellaneous digital
50 LRCLK Miscellaneous
51 MCLK/INT2 Miscellaneous
52 DVDD Power
53 SCL Miscellaneous digital
54 SDA Miscellaneous digital
55 INT1 Miscellaneous digital
56 RESET Miscellaneous digital
57 PVDD Power
58 XTALP Miscellaneous analog
59 XTALN Miscellaneous analog
60 DVDD Power
61 CEC Digital input/output
62 DDCA_SCL HDMI input
63 DDCA_SDA HDMI input
64 RXA_5V HDMI input
Description
Line Locked Output Clock for the Pixel Data (Range is 13.5 MHz to 162.5 MHz).
Video Pixel Output Port.
Video Pixel Output Port.
Video Pixel Output Port.
Video Pixel Output Port.
Video Pixel Output Port.
Video Pixel Output Port.
Video Pixel Output Port.
Video Pixel Output Port.
Digital I/O Supply Voltage (3.3 V).
Video Pixel Output Port.
Video Pixel Output Port.
Video Pixel Output Port.
Video Pixel Output Port.
Video Pixel Output Port.
Digital Core Supply Voltage (1.8 V).
Video Pixel Output Port.
Video Pixel Output Port.
Video Pixel Output Port.
Digital I/O Supply Voltage (3.3 V).
DE (data enable) is a signal that indicates active pixel data.
HS is a horizontal synchronization output signal.
VS is a vertical synchronization output signal. FIELD is a field synchronization output
signal in all interlaced video modes. VS or FIELD can be configured for this pin. The
ALSB allows selection of the I
Audio Output Pin. Pin can be configured to output SPDIF Digital Audio Output (SPDIF)
or Time-Division-Multiplexed I
A dual function pin that can be configured to output Audio Serial Clock or an
Interrupt2 signal.
Audio Left/Right Clock.
A dual fuction pin that can be configured to output Audio Master Clock or an
Interrupt2 signal.
Digital Core Supply Voltage (1.8 V).
I 2 C Port Serial Clock Input. SCL is the clock line for the control port.
2
I C Port Serial Data Input/Output Pin. SDA is the data line for the control port.
Interrupt. This pin can be active low or active high. When status bits change, this pin is
triggered. The events that trigger an interrupt are under user configuration.
System Reset Input. Active low. A minimum low reset pulse width of 5 ms is required
to reset the ADV7611 circuitry.
PLL Supply Voltage (1.8 V).
Input Pin for 28.63636 MHz Crystal or an External 1.8 V, 28.63636 MHz Clock Oscillator
Source to Clock the ADV7611.
Crystal Input. Input pin for 28.63636 MHz crystal.
Digital Core Supply Voltage (1.8 V).
Consumer Electronic Control Channel.
HDCP Slave Serial Clock Port A. DDCA_SCL is a 3.3 V input that is 5 V tolerant.
HDCP Slave Serial Data Port A. DDCA_SDA is a 3.3 V input that is 5 V tolerant.
5 V Detect Pin for Port A in the HDMI Interface.
Rev. A | Page 12 of 184
Hardware User Guide
2
C address.
2 S.