Analog Devices Advantiv ADV7611 Hardware User's Manual page 176

UG-180
DPLL_SLAVE_ADDR[6:0], IO, Address 0xF8[7:1]
2
Programmable I C slave address for DPLL map
Function
DPLL_SLAVE_ADDR[6:0]
0x00 (default)
0xXX
2
Protocol for Main I C Port
The system controller initiates a data transfer by establishing a start condition, defined by a high to low transition on SDA while SCL
remains high. This transition indicates that an address/data stream will follow. All peripherals respond to the start condition and shift
the next eight bits (7-bit address and R/W bit). The bits are transferred from MSB down to LSB. The peripheral that recognizes the
transmitted address responds by pulling the data line low during the ninth clock pulse. This is known as an acknowledge bit. All other
devices withdraw from the bus at this point and maintain an idle condition.
In the idle condition, the device monitors the SDA and SCL lines for the start condition and the correct transmitted address. The R/W bit
determines the direction of the data. A Logic 0 on the LSB of the first byte means that the master will write information to the peripheral.
A Logic 1 on the LSB of the first byte means that the master will read information from the peripheral.
Each of the ADV7611 maps acts as a standard slave device on the bus. The data on the SDA pin is eight bits long, supporting the 7-bit
addresses plus the R/W bit. It interprets the first byte as the map address and the second byte as the starting subaddress. The subaddresses
auto-increment, allowing data to be written to or read from the starting subaddress. A data transfer is always terminated by a stop
condition. The user can also access any unique subaddress register on a one-by-one basis without having to update all the registers.
Stop and start conditions can be detected at any stage during the data transfer. If these conditions are asserted out of sequence with
normal read and write operations, these cause an immediate jump to the idle condition. During a given SCLK high period, the user
should issue only one start condition, one stop condition, or a single stop condition followed by a single start condition. If an invalid
subaddress is issued by the user, the ADV7611 does not issue an acknowledge and returns to the idle condition.
If the user exceeds the highest subaddress in auto increment mode, the following actions are taken:

In read mode, the highest subaddress register contents continue to be output until the master device issues a no acknowledge. This
indicates the end of a read. A no acknowledge condition is where the SDA line is not pulled low on the ninth pulse.

In write mode, the data for the invalid byte is not loaded into any subaddress register. A no acknowledge is issued by the ADV7611
and the part returns to the idle condition.
SDATA
SCLOCK
START
WRITE
S SLAVE ADDRESS
SEQUENCE
READ
S SLAVE ADDRESS
SEQUENCE
S = START BIT
P = STOP BIT
A(S) = ACKNOWLEDGE BY SLAVE
A(M) = ACKNOWLEDGE BY MASTER
A(S) = NO ACKNOWLEDGE BY SLAVE
A(M) = NO ACKNOWLEDGE BY MASTER
Description
Map not accessible
DPLL Map Slave address
1-7
S 8 9
ADDR R/W ACK
A(S) SUBADDRESS
LSB = 0
A(S) SUBADDRESS
Figure 67. Read and Write Sequence
1-7
8 9
SUBADDRESS ACK
Figure 66. Bus Data Transfer
A(S) DATA A(S)
LSB = 1
A(S) S SLAVE ADDRESS
Rev. A | Page 176 of 184
Hardware User Guide
1-7
8 9 P
DATA ACK STOP
...
DATA A(S)
...
A(S) DATA A(M)
P
DATA A(M) P