Analog Devices Advantiv ADV7611 Hardware User's Manual page 128

UG-180
END_VS_EVEN[3:0] , Addr 44 (CP), Address 0x89[3:0]
A control to shift the position of the trailing edge of the Vsync output by the CP core.
This register stores a signed value in a twos complement format. SEND_VS_EVEN[3:0] is the number of lines by which the trailing edge
of the Vsync is shifted (for example, 0x0F corresponds to a shift of 1 line toward the active video, 0x01 corresponds to a shift of 1 line
away from the active video).
Function
END_VS_EVEN[3:0]
0x0 to 0x7
0x8 to 0xF
DE Timing Controls
DE_H_END[9:0] , Addr 44 (CP), Address 0x8B[1:0]; Address 0x8C[7:0]
A control to vary the trailing edge position of the DE signal output by the CP core.
This register stores a signed value in a twos complement format. The unit of DE_H_END[9:0] is one pixel clock.
Function
DE_H_END[9:0]
0x200
0x3FF
0x000 (default)
0x001
0x1FF
DE_H_START[9:0] , Addr 44 (CP), Address 0x8B[3:2]; Address 0x8D[7:0]
A control to vary the leading edge position of the DE signal output by the CP core.
This register stores a signed value in a twos complement format. The unit of DE_H_START[9:0] is one pixel clock.
Function
DE_H_START[9:0]
0x200
0x3FF
0x000 (default)
0x001
0x1FF
DE_V_START[3:0] , Addr 44 (CP), Address 0x8E[7:4]
A control to vary the start position of the VBI region.
This register stores a signed value represented in a twos complement format. The unit of DE_V_START[9:0] is one line.
Function
DE_V_START[3:0]
1000
1111
0000 (default)
0001
0111
Description
The trailing edge of the even Vsync is shifted toward the active video.
The trailing edge of the even Vsync is shifted away from the active video.
Description
−512 pixels of shift
−1 pixel of shift
Default value (no shift)
+1 pixel of shift
+511 pixels
Description
−512 pixels of shift
−1 pixel of shift
Default value (no shift)
+1 pixel of shift
+511 pixels
Description
−8 lines of shift
−1 line of shift
Default
+1 line of shift
+7 lines of shift
Rev. A | Page 128 of 184
Hardware User Guide