Analog Devices Advantiv ADV7611 Hardware User's Manual page 147

Hardware User Guide
5. Another message is received. The receiver module checks to see which of the three buffers are available, starting with Buffer 0. In this
example, Buffer 0 has been read out already by the host processor and is available so the new message is stored in Receive Buffer 0. At
this time the timestamp for Receive Buffer 1 is adjusted to 0b01 to show that it contains the first received message, and a timestamp
of 0b10 is assigned to Receive Buffer 0 to show that it contains the second received message. If the corresponding interrupt mask bit
is set the CEC_RX_RDY0_ST bit goes high and an interrupt is generated to alert the host processor that a message has been received.
6. Another message is received. This message is stored in Receive Buffer 2 (Buffer 0 and Buffer 1 are full). Time stamp 0b11 is assigned
to Receive Buffer 2 to show that it contains an unread message that was the third to be received. If the corresponding interrupt mask
bit is set the CEC_RX_RDY2_ST bit goes high and an interrupt is generated to alert the host processor that a message has been
received. At this time all receive buffers are full and no more messages can be received until the processor reads at least one message.
7. The host processor responds to the interrupts, or polls the timestamps and realizes that messages have been received, and reads the
three time stamps. The buffer with the earliest time stamp should be read first, therefore Receive Buffer 1 is read first, followed by
Receive Buffer 0 and then Receive Buffer 2. Once the messages are read the processor sets CEC_RX_RDY0_CLR, CEC_RX_RDY1_CLR,
and CEC_RX_RDY2_CLR. The time stamps for all three buffers are reset to 0b00 .
ANTIGLITCH FILTER MODULE
This module is used to remove any glitches on the CEC bus to make the CEC input signal cleaner before it enters the CEC module. The
glitch filter is programmable through the CEC_GLITCH_FILTER_CTRL register. The register value specifies the minimum pulse width
that will be passed through by the module. Any pulses with narrower widths will be rejected. There is a CEC_GLITCH_FILTER_CTRL +
1 number of clock delays introduced by the antiglitch filter.
CEC_GLITCH_FILTER_CTRL[5:0] , Addr 80 (CEC), Address 0x2B[5:0]
The CEC input signal is sampled by the input clock (XTAL clock). CEC_GLITCH_FILTER_CTRL specifies the minimum pulse width
requirement in input clock cycles. Pulses of widths less than the minimum specified width are considered glitches and will be removed by
the filter.
Function
CEC_GLITCH_FILTER_CTRL[5:0]
000000
000001
000010
...
000111 (default)
...
111111
Description
Disable the glitch filter
Filter out pulses with width less than 1 clock cycle
Filter out pulses with width less than 2 clock cycles
...
Filter out pulses with width less than 7 clock cycles
...
Filter out pulses with width less than 63 clock cycles
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