Design Considerations - Quectel SG865W Series Hardware Design

CAM0_AFVDD_EN
Module
NOTE
CAM0_AFVDD_EN pin can be multiplexed from UART17_CTS.

4.14.1. Design Considerations

⚫
Special attention should be paid to the pin definition of LCM/camera connectors. Assure the module
and the connectors are correctly connected.
⚫
MIPI is high speed signal traces, supporting maximum data rate up to 2.5 Gbps. The differential
impedance should be controlled to 85 Ω. Additionally, it is recommended to route the trace on the
inner layer of PCB, and do not cross it with other traces. For the same group of DSI or CSI signals, all
the MIPI traces should keep the same length.
⚫
To avoid crosstalk, spacing the lanes according to the following rules:
a) Intra-pair P to N: 1 × trace width
b) lane to lane: 1.5 × trace width
c) lanes to all other signals: 2.5 × trace width
⚫
It is recommended to select a low capacitance TVS for ESD protection and the recommended
parasitic capacitance should be below 0.5 pF.
⚫
Route MIPI traces according to the following rules:
a) The total trace length should be less than 150 mm with -6.5 dB total insertion loss and -3.5 dB
cable insertion loss for 2.5 Gbps;
b) Control the differential impedance to 85 Ω ± 10 %;
c) Control intra-pair length matching (P/N) within 0.7 mm;
d) Control inter-lane length matching within 1.4 mm.
SG865W_Series_Hardware_Design
VPH_PWR
R1
C1
2.2 μ F
100K
Figure 25: Reference Design of Camera Power Supply
LDO7C_2V85
NM
LDO_IC
C2
2.2 μ F
Smart Module Series
CAM0_AF_VDD_2V8
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