Llc Controls; Dll On Llc Clock Path - Analog Devices ADV7610 Hardware User's Manual

UG-438
OP_SWAP_CB_CR, IO, Address 0x05[0]
A control for the swapping of Cr and Cb data on the pixel buses.
Function
OP_SWAP_CB_CR
0 (default)
1
OP_SWAP_CB_CR swaps the order in which Cb and Cr are interleaved in the output data stream. It caters for cases in which the data on
Channels B and C are swapped. It is effective only if OP_FORMAT_SEL[7:0] is set to a 4:2:2 compatible output mode.
Note: It has no effect for 24-bit SDR modes and DDR modes.

LLC CONTROLS

The ADV7610 has a limited number of adjustment features available for the line locked clock (LLC) output. The polarity of the LLC can
be inverted and the LLC of the output driver can be tristated. Controls also exist to skew the LLC versus the output data to achieve
suitable setup and hold times for any back end device.
The LLC controls are as follows:
•
INV_LLC_POL
•
TRI_LLC
•
LLC_DLL_EN
•
LLC_DLL_MUX
•
LLC_DLL_PHASE[4:0]

DLL ON LLC CLOCK PATH

A delay locked loop (DLL) block is implemented on the LLC clock path. This DLL allows the changing of the phase of the output pixel
clock on the LLC pin.
LLC_DLL_DOUBLE, IO, Address 0x19[6]
A control to double LLC frequency.
Function
LLC_DLL_DOUBLE
0 (default)
1
Adjusting DLL Phase in All Modes
LLC_DLL_EN, IO, Address 0x19[7]
A control to enable the DLL for the output pixel clock.
Function
LLC_DLL_EN
1
0 (default)
LLC_DLL_MUX, IO, Address 0x33[6]
A control to apply the pixel clock DLL to the pixel clock output on the LLC pin.
Function
LLC_DLL_MUX
0 (default)
1
Description
Outputs Cr and Cb as per OP_FORMAT_SEL
Inverts the order of Cb and Cr in the interleaved data stream
Description
Normal LLC frequency
Double LLC frequency
Description
Enables LLC DLL
Disables LLC DLL
Description
Bypasses the DLL
Muxes the DLL output on LLC output
Rev. 0 | Page 24 of 184
Hardware User Guide