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BUS DEFINITION
Back Side
No.
73
74
7 5
76
PSYNC
77
2 - 1 6
SYMBOL
NAME
PINT
INTERRUPT
REQUEST
PHOLD
HOLD
PRESET
RESET
SYNC
PWR
WRITE
Mother Board
User Guide
FUNCTION
The processor recog
nizes an interrupt
request on this line
at the end of the
current instruction
or while halted. If
the processor is in
the HOLD state or
the Ihterrupt Enable
flip-flop is reset,
it will not honor
the request
Processor command
input signal which
requests the proces
sor to enter the
HOLD state; allows
an external device
to gain control of
address and data
buses as soon as the
processor has com
pleted its use of
these buses for the
current machine cycle
Processor command
input; while activa
ted the content of
the program counter
is cleared and the
instruction register
is set to 0
Processor control
output provides a
signal to indicate
the beginning of each
machine cycle
Processor control
output used for mem
ory write or I/O out
put control; con
tinued next page.
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