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USER GUIDE
Request for an interrupt appears at the PIC-8 board in the
form of one of the eight priority interrupt request lines
being pulled to a logic 0 level.
nize that one or more interrupts are being requested and it
will determine which multiple request has the highest priority.
The eight priority levels are numbered 0 through 7, with 7
being the highest priority.
est current interrupt request is then compared against the
value stored in the current priority status register in bits
0, 1 and 2.
If the currently-requested priority level is
equal to or lower than the value stored in the current
priority status register, no interrupt will be generated.
If the priority interrupt being requested is 0 and the
current priority status register contains a 0, no interrupt
will be generated.
priority status register, then only interrupt levels 6 and
7 would generate an interrupt.
lower would not be acted upon at thi§ time.
If the priority interrupt being requested is 0, and the
current priority status register contains a 0, no interrupt
would be generated as the priority level is not greater than
that stored in the current priority status register.
the current priority status register data bit 3 is written
as a 1, the compare to the current priority status register
is overridden, and the request for an interrupt priority 0
is acted upon and an interrupt to restart position 0 is
generated.
If other priority level interrupts are requested during the
time that data bit 3 has been written as a 1 in the current
priority status level, then the highest priority interrupt
requested will be acted upon.
At any time, if there is more than one priority level of
interrupt being requested, only the highest priority level
is acted upon, and any interrupt requests not serviced must
be held present until the system can return to them.
After each interrupt has been generated, and the processor
has responded to it, it is necessary that the current
priority status register be restored to either the same or
a different value; otherwise, no further interrupts will be
generated.
The 8214 chip will recog
The priority level of the high
Thus, if a 5 were stored in the current
Interrupt levels 5 and
PIC-8
User Guide
Revision 3
If
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