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TRUE LOC.
CONTENTS
F000
0 0
7
F001
F000
0 1
7
F001
E
1
0 0 0
7
F001
Thus, Phase III detects our error.
on how to find the error.
1.
Between steps 1 and 4097, several milliseconds pass
without accessing location F000.
the data in F000 could go away and generate a Phase III
error.
This can be found by DEPOSITing into the bad
location and EXAMINEing it to see if it changes.
reason Phase I doesn't catch this is that it reads
3.5 /is after it writes, so the data doesn't have time
to deteriorate.
2.
If address line 0 were stuck at 1, the same results
would appear in Phase III.
from this test what the line is stuck at.
3.
If Phase II or III fails, the bad address bits, are the
ones where the "supposed to be" data and the "read back"
data differ.
the high
bits of address.
8
these represent the low
RESPONDS TO:
F000, F001
nothing
F000, F001
nothing
F000, F001
expecting nothing - and detect an error.
(Try it.)
If the error was Phase II? these represent
If the error was Phase III,
bits.
8
RAM 4A
Board Tester
Step 1: Write 00 into F000
Step 2: Write 01 into F001
Step 4097: Read F000,
Now for some observations
If RAM is volatile,
You can't tell
The
6 - 2 7
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