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The STATUS WORD DISABLE line (SSWDSB, Pin 53 backplane)
is gated to insure that no conflicts are created between
the bi-directional bus drivers on the MPU and CP-A boards.
This signal is controlled by the same gating , that places
the high order address switch values on the data bus
for a front panel (address hex FF) read.
The STATUS WORD DISABLE line. Pin 53 in the backplane,
is also run by the signal which puts the high order
address switches onto the data bus for the port FF read
instruction so that the bi-directional data bus is not
being driven by the bi-directional drivers on the MPU
board at the same time that the front panel is insert
ing the switch information on the data bus.
The RESET switch directly grounds the RESET line on the
backplane which is detected by the MPU board and pro
cessed to form a RESET pulse which re-appears on the
backplane as a Power On Clear.
When the RESET switch is thrown to EXTERNAL CLEAR, the
switch directly grounds the EXTERNAL SWITCH line on the
backplane.
There is a diode between the RESET line and
the EXTERNAL CLEAR line so that during a reset operation
an EXTERNAL CLEAR is also generated.
CP-A
Theory of Operations
Revision 1
4 - 7
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