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BUS DEFINITION
Front Side
N o .
22
ADDR DSBL
23
DO DSBL
24
25
26
PHLDA
27
28
2 - 1 2
SYMBOL
NAME
ADDRESS DISABLE
DATA OUT DISABLE
02
Phase 2 Clock
Phase 1 Clock
01
Hold Acknowledge
PWAIT
WAIT
PINTE
INTERRUPT ENABLE
Mother Board
User Guide
FUNCTION
Allows the buffers
for the 16 address
lines to be tri-
stated
Allows the bidirec
tional data bus
drivers for the 8
data lines to be tri-
stated for both in
put and output data
buses
Processor control
output signal which
appears in response
to the HOLD signal;
indicates that the
data and address bus
will go to the high
impedance state on
the 8080. Note;
ADDR DSBL and DO DSBL
must be driven to
ri-state the system
bus
Processor control
output signal which
acknowledges that the
processor is in a
WAIT state
Processor control out
put signal indicating
interrupts are en
abled: may be set or
reset by El and DI
instruction and inhib
its interrupts from
being accepted by the
CPU if it is reset
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