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THEORY OF OPERATION
The board enable is the output of the 74LS30 in position
C9.
Input to this 8 input NAND gate is the true or com
plement address bits 2 through 6, according to how they
are jumpered.
The input and output status bits are logically
ORed and the output or its complement is also jumpered
to the NAND gate in position C9.
I/O reference instructions or these two inputs to the NAND
gate are taken from the complement of the status input or
output instruction and the high address line which comes
from the 74LS30 in position C6.
tion C6 is active when all the high order of address bits
8 through 15 are true, that is, high.
their complements are fed into a one-of-4 decoder con
sisting of the 7427 in position and part of the 7402 in
position Cll along with one inverter.
Also as a condition in this one-öf-four decoder is the
board enable.
The outputs of this one-of-four decoder
are fed directly to the enable pins on the respective
8212 input or output ports.
8080 system is driven directly from the output of the
four input latches.
enabled only when the chip is selected by the one-of-four
decoder.
The DATA OUTPUT bus in the IMSAI 8080 goes directly to the
four.8212 output ports.
the input ports is connected to the PROCESSOR DATA BUS-IN
signal such that the data is placed on the IMSAI 8080 bus
during the time that the processor wishes to read it.
other device select line in output port 8212's is driven
by the ORed condition of the PROCESSOR WRITE STROBE or
FRONT PANEL WRITE STROBE, these coming from pins 77 and 68
on the IMSAI 8080 back plane respectively.
DATA BUS-IN signal appears on pin 78 of the IMSAI 8080
back plane.
Handling the interrupt levels from the four input and four
output ports requires only the interrupt select jumper
socket in position 2 so that the appropriate interrupt
levels which are already originated by the 8212 chips
can be connected as desired to the proper priority interrupt
line on the IMSAI 8080 back plane.
interrupt function is affected by the PIC-8 board, the
Priority Interrupt/Clock board.
These two are used for
This NAND gate in posi
The DATAIN bus on the IMSAI
This is a tri-state output and is
The second enable line on each of
The remainder of the
PIO 4, Rev. 2
Theory of Operation
Address 0 and 1 and
The
The PROCESSOR
8
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