Download Print this page

IMS IMSAI 8080 User Manual page 414

Advertisement

In the input data stream from the recorder, when the pre­
sent data bit is the same as the previous data bit, a se­
cond transition occurs at approximately the eigth clock
cycle.
Because the one-shot is disabled, this transition
will not be detected.
occur after the twelfth clock cycle, enabling the counters,
and causing the data leyel to be read four clock cycles
later, as described above.
Because two transitions have occurred since the last time
the level was read, the new level and the previous level
will be the same, which they should be to represent data
bits which are the same.
Read Clock
The pulses from the one-shot will occur once per bit time
because of the disabling described above, and are used to
generate the clock for the shift register.
represents a reconstruction of the original write clock, one
that is dependent only on transitions read from the tape,
so that the tape format is inherently self-clocking, and
immune to even large variations in tape speed.
However, the next transition will
MIO
Theory of Operation
This clock

Advertisement

loading