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for channel B control bytes would be hex 5 or octal 05.
Address b i t 3 (A3) selects the board control I/O port.
Whe n address b i t 3 (A3) is high, the control port will be
enabled.
Thus, when use is being made of the control port,
the lower 4 bits of address would normally be heix 8 or
octal 10.
The control I/O byte selected b y address b i t 3 is divided
into the upper 4 bits and the lower 4 bits.
bits, 0 through 3, serve the channel A serial I/O circuit.
The upper four bits, 4 through 7, serve the second I/O
channel B functions.
respectively, control the interrupt enable separately for
each channel.
W h en this bit is a 1, the interrupts are
enabled and the processor will receive and interrupt when
ever any one of the following 4 lines are active:
transmitter ready line, the transmitter empty line, the
receiver ready line, a n d the sync detect line.
If bits 0 or 4 (as appropriate to channel A or B) are made
0, then no interrupts will be generated from the affected
channel.
Bits 1 and 5 serve channel A and B, respectively,
to output the carrier detect signal.• This is operative
only when the -jumper in jumper socket BJ has selected the
board to act as the originator of the carrier detect line.
Bits 2, 3, and 6, and 7 are not functional in the output
mode for the SIO control byte.
the SIO control byte, bits 0, 1, 4 and 5 are not functional.
These 4 bits will always be read as a 1.
Bits 2 and 6 read the condition of the carrier detect re
ceiver for channels A and B, respectively.
operative only when jumper socket BJ is jumpered to read
the condition of the carrier detect line.
Bits 3 and 7 serve channel A and B, respectively, to read
the condition of the clear-to-send (CTS) control signal.
This is provided because it is not possible to read the
condition of CTS through programmed input from the 8251.
9
22
Bits 0 a nd 4, for channel A and B
When an input is read from
SIO 2 Board Rev. 3
Users Guide
Edition 2
The lower 4
the
The signal is
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