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which should now appear on the lights on the data bus
indicators.
As the SINGLE STEP switch is operated again,
permitting the processor to complete the fetch of the
jump instruction, and start the next cycle of executing
that jump instruction, we find that the processor is
reading the low half of the address from memory position
5.
The status byte shows the MEMR and WO lights lit,
and the Ml light
If the SINGLE STEP, switch is operated once again, it will
be seen that the processor is reading the high address
byte previously stored in memory location 6.
The next operation of the SINGLE STEP switch permits
the processor to complete the execution of that jump
instruction, which is instructing the processor to
take its next instruction to be executed not from memory
position 7 but from memory position 0 as was stored in
the two bytes following the jump instruction.
The Address Bus lights should now be all off indicating
that the processor is indeed fetching the next
instruction from memory location 0.
show the pattern that we wrote in memory position 0 as
the input instruction.
of the loop in Test Program 1.
SINGLE STEP switch will let the processor step through the
execution of the loop additional times and each time
through the loop it is possible to set a different
pattern in the left hand group of switches to be read in
and later to be written out to the PROGRAMMED OUTPUT light;
The RUN/STOP switch can be momentarily raised to the RUN
position and released.
run at the full clock speed which will result in the loop
being executed roughly 50,000 times every second.
as any of the switches in the left hand group of eight are
moved while the program is running, the machine reads
the new position essentially instantly and displays it -
in the PROGRAMMED OUTPUT port above.
It may have been puzzling that the lights in the PROGRAMME]
OUTPUT port seem to indicate the opposite of what might
have been expected when a bit was read in as a 1 and outpu-
to the PROGRAMMED OUTPUT port.
example of the way logic design has been affected by
the appearance of large scale integration and micro
processors.
While it would have been entirely possible -
IMSAI 8080
General Assembly and
Test Instructions
is off at this time.
We have now completed one cycle
Further operations of the
This will permit the processor to
This will serve as an
The Data Bus should
Thus,
39
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