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which is a digital form of the received data.
shows the output of the zero crossing one-shot detector
as if it were never disabled.
gate for this zero crossing detector.
put of the 74LS74 flip-flop.
high in the counter.
strobe the data on the return.
structed data stream.
The reader should become familiar with the diagram before
proceeding on with the discussion.
arity of the written data and/or the digital recovered data
output of the 8T20 can be inverted when it goes through the
EXCLUSIVE OR gates.
dress Jumper are used to invert the output and. input data,
respectively.
This option is provided so that the proper
data will be fed into your recorder and returned from it
independently of the phase*on which the recorder operates.
Pin 1 of the 8T20 fed back through R44 provides the hyster
esis for the 8 T20.
popular recorders.
value should be lowered to increase the hysteresis and
raised to decrease it.
The shift register used in this section is a 74LS395.
provides both the tri-state outputs for gating onto the in
ternal data bus and the cascadeable output for forming an
8-bit shift register.
the two 74LSl63s and the 74LS293.
jumper-selected so that they reload at sixteen times the
required data frequency.
put of the 74LS163s to generate timing for the read and
write circuitry.
Cassette Read Operation
In read operation, the first transition received from the
recorder starts the CRI clock.
the eight-bit shift register Is clocked, loading the cur
rent level of the input data into the register.
twelve clock cycles, the 74LS293 is put into reset, and the
74LS163s are put into LOAD mode, thus presetting and holding
them.
The entire circuit then idles until the next input
transition, which again allows the counters to run.
Referring again to Figure I, line 8 (labelled zero crossing)
represents the output of the 8T20 one shot as if it were
never disabled.
every zero-crossing transition input from the recorder.
The one-shot disable flip-flop (U36), however,
the one-shot from detecting a transition from the time the
first transition starts the counters until the twelfth clock
cycle, when the clocks are disabled.
Line 9 shows the disable
Line 10 shows bit 4 coming
The leading edge of bit 4 is used to
Line 11 shows the recon
Switches 7 and 8 in the External Ad
The given value of R44 works with most
If adjustment should be necessary, its
The timing generator consists of
The 74LS293 divides down the out
After four clock cycles,
That is, it generates a short pulse for
MIO
Theory of Operation
Line 8
This is the out
Notice that the pol
The 74LSl63s should be
After
prevents
This
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