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THEORY OF OPERATION
The PI06 Board is enabled by having its address (as jumpered
in the Address Jumper Sockets) appear on the microprocessor
address lines during an input or output instruction.
this occurs, the outputs of the Address Jumper Socket will all
be high, causing the output of the 74LS30 at location C7 to be
low which is the true state of the board enable signal "/BDENA".
This signal is buffered by an 8T97 and passed on to connectors
J2 and J3 as "/HIADD".
signal is the OR of the microprocessor status bits "SINP" and
"SOUT" which are the strobes used to indicate input instruc
tion and output instruction respectively.
The board enable signal is further AND'ed with address lines
2 and 3 to create the 8255 chip selects "/CSO" and "/CSl".
This is done in three section of the 74LS32 in location C
To get either of the chip'selects true, address line 3 must
be low.
Address line 2 low allows /CSO to be true while ad
dress line 2 high allows /CSl to be true.
Once an 8255 is selected, it becomes responsive to the I/O
command to transfer data to it or from it.
tions of which the 8255's are capable are selected by the ap
propriate combination of address bits
to 8255 port address inputs AO and Al (pins 9 and
After buffering through 8T97's, the processor's read (PDBIN)
and write (/PWR) strobes are wired to the read and write lines
of the 8255's.
the 8255 to create the proper polarity read signal.
External clear (/EXT CLR) from the processor front panel
switch and power on clear (/POC) from the processor are OR'ed
together to provide the reset signal to the 8255's and the J2
and J3 connectors.
Four 8216's are utilized to provide two levels of buffering
for the data bus.
cessor and the 8255's.
8255's and the J2 and J3 connectors.
(/BDENA) allows the microprocessor data bus to be connected
to the 8255's data bus.
is high, the 8255 bus is connected to the J2 and J3 connectors.
The external board enable signal available to the J2 and J3
connectors (/BDEN) enables both pairs of 8216's which allow
the microprocessor data bus to be bussed to the J2 and J3
connectors.
All other processor signals brought to the J2, J3 and J4
connectors are buffered by 8T97's.
+
, +18 and -18 volts and GROUND are bussed directly from the
8
J1 connector (which plugs into the processor motherboard) to
the J2 and J3 connectors.
Also, AND'ed into the board enable
The read signal is inverted before reaching
The first pair buffer between the micropro
The second pair buffer between the
In addition, if address line 3 (A3)
PI06
Theory of Operation
Revision 0
The various func
and
which are bussed
0
1
).
8
The board enable signal
The processor voltages
When
.
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3 - 3
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