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The EXAMINE switch, can again be raised momentarily with the
address switches all down, to return the machine to position
0, once it has been determined that all lines listed in Test
Program One are stored correctly in the memory.
Now we can single-step through this program and watch the
operation of the machine.
with the correct instruction on the data bus, and the MEMR,
Ml and WO lights lit in the status byte, the processor is
reading the first instruction out of memory into the proces
sor for execution.
pressed or raised once, it will permit the processor to
complete its cycle and begin the next cycle.
lights will show position 1, the data bus will show all ones
corresponding to the bit pattern in the Test Program, and the
status byte will show MEMORY READ and WO.
light in a status byte indicates that the processor is no
longer fetching an instruction to execute, but rather this
cycle it is fetching the address for the instruction which
it has already stored internally.
If the SINGLE-STEP switch is operated once again, the address
bus lights will all be lit.
WO and the data bus will at first show no lights on.
or more switches in the left hand group of eight switches is
now raised or lowered, the corresponding light on the data bus
indicators will turn on or off.
ing the first instruction which was an input data from address
FF hex (377 octal) which is the address for the programmed
input port on the front panel.
with this address the processor is able to read the position of
the eight switches in the left hand group.
read is indicated by the lighfs in the address bus and, on
input or output instructions, the address appears in both
groups of eight lights on the address bus.
address, all the lights in the address bus are lit.)
The switches in the left hand group should be left in the
position of some up and some down to provide a recognizable
pattern before continuing.
left hand group of switches, the single step switch can be
operated once more permitting the processor to complete the
execution of the input instruction, and begin the next cycle.
Having completed the input instruction, the next cycle will be
a fetch cycle during which the processor reads the next
instruction to be executed, which it will find in memory
address position 2.
positon 2 (bit 1 on and all others off), and the data bus
should indicate the bit pattern listed on line 3 of Test
Program 1 for address position 2.
instruction.
IMSAI 8080
General Assembly and
Test Instructions
With the-machine sitting at 0
If the SINGLE-STEP switch is either de
The status byte will show INP and
The processor is now execut
By means of this instruction
With the pattern left in the
The address bus lights should now show
This is the output
The address bus
The lack of an MI
If one
(The address being
Thus, for this
37
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