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stops the processor during the fetch of the designated
memory byte-
Similarly, the DEPOSIT switch, when operated, produces
a pulse from the DEPOSIT one-shot which is buffered
to the MEMORY WRITE line on the backplane.
edge of this pulse also starts a second one-shot with
a much longer period which puts the data from the data
switches on to the data bus for the duration of the
longer pulse.
The DEPOSIT one-shots are triggered
either by the operation of the DEPOSIT switch or by
the trailing edge of the DEPOSIT NEXT one-shot so that
the DEPOSIT function will operate at the end of the
EXAMINE NEXT cycle.
The 7427 gate in U15.5 is used to insure that during
the time the front panel is inserting any information
on the bi-directional data bus, the MPU-A board's bi
directional data bus driver is not also trying to drive
the bus at the same time.
The inputs to this gate are the DATA-ON line, the EXAMINE
NEXT line and the EXAMINE line.
functions during which the front panel is transferring
data or instructions to the b u s .
The inputs to the 7405 open-collector inverter bus
drivers are the lines NO-OP, C3, HAD, and LAD.
levels are ANDed with the PDBIN signal so that the
information appears on the bus during the time the
processor is expecting to see it there.
The input port from the high order address switches is
implemented simply by decoding the
and ANDing it with the DBIN signal so that
values appear on the data bus during the time that the
processor is expecting information from the port FF.
The same address decode signal is ANDed with the STATUS
OUT line to enable the 8212 8 bit latch which drives
the PROGRAMMED OUTPUT indicators.
the bi-directional data bus is then latched onto the
output port at the time of the processor write strobe.
4 - 6
CP-A
Theory of Operations
Revision 1
The leading
These are the three
These
address FF
switch
The information on
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