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function is identical to the P-READY line used by the
memory and I/O boards.
for use of the front panel to avoid conflicts of two
gates driving the same backplane line).
of these functions, the processor is permitted to
execute an instruction, and then is stopped in the
next cycle in a manner similar to the RUN/STOP flip-
flop cycle described earlier.
For the SINGLE STEP function, a one-shot, triggered by
the SINGLE-STEP switch, is used to produce a pulse and
the trailing edge of that pulse is used to set a flip-
flop which controls the SINGLE STEP line.
the processor to execute the present instruction.
SINGLE STEP flip-flop is reset by the occurrence of the
sync pulse on the following instruction, thus causing
the SINGLE STEP level to be removed and the processor
to stop on the following cycle.
The EXAMINE-NEXT flip-flop is similarly controlled by
the leading edge of a pulse from a one-shot driven by
either the DEPOSIT NEXT or EXAMINE NEXT switch.
output of the flip-flop is used both to put the NO-OP
(hex 00 or octal 000) onto the bi-directional data bus,
and also to provide the READY signal so that the pro
cessor will execute the instruction.
the sync pulse on the following cycle, thus stopping
the processor again.
The EXAMINE function involves a 4-step sequence produced
by two flip-flops arranged as a counter. The pulse pro
duced by the EXAMINE switch's one-shot starts the
counter and on the first count, the jump instruction
is inserted on the data bus.
the two bit counter, the lower and upper address byte
are inserted on the data bus in turn, and on the 4th
count (that is, when the counter is tack to 0), the
processor is again stopped by the removal of the READY
line.
Thus, the EXAMINE logic provides the processor
with the jump instruction and the two address bytes
that the processor expects after a jump instruction and
CP-A
Theory of Operations
Revision 1
The X-READY line is reserved
It is reset by
On successive counts of
During each
This permits
The
The
4 - 5
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