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BUS DEFINITION
Front Side
NO.
46
47
48
49
50
Back Side
No.
51
52
53
SSW DSB
54
EXT CLR
2 - 1 4
SYMBOL
NAME
SNIP
INP
SMEMR
MEMR
SHLTA
HLTA
CLOCK
CLOCK
GND
GROUND
SYMBOL
NAME
+8V
+8 volts
-16V
-16 volts
SENSE SWITCH
DISABLE
EXTERNAL CLEAR
Mother Board
User Guide
FUNCTION
Status output signal
which indicates that
that the address bus
contains the address
of an input device
and the input data
should be placed on
the data bus when
PDBIN is active
Status output signal
which indicates that
the data bus will be
used for memory read
data
Status output signal
which acknowledges a
HALT instruction
2 MHz clock signal
FUNCTION
Unregulated input to
5v regulators
Negative unregulated
voltage
Disables the data in
put buffers so the
input from the sense
switches may be
strobed onto the bi
directional data bus
Clear signal for I/O
devices (front panel
switch closure to
ground)
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