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MIO SPECIFICATIONS
Basic Configuration
1.
The MIO board uses four I/O ports and is available with
the following I/O interfaces:
Two parallel (PIO) ports
One control (CTL) port
One cassette recorder (CRI) port
One serial (SIO) port
2.
There are three 26 pin edge connectors on the top of
the board, two for the PIO ports and one for the SIO
port.
The SIO pin assignments are compatible with the
standard EIA connectors.
are the same as the PIO 4 port 0 input pin numbers, and
the PIO output pin numbers are the same as the PIO 4
port 1 output pin numbers.
3.
The board address (one of the 64 possible groups of
four I/O ports) and the order of the addressing of the
four ports on the board are jumper-selectable.
4.
Interrupt requests are jumper-selectable to PIC-8
and CPU lines.
5.
The operation of the individual ports is as follows:
A)
SIO
1.
Baud rate is jumper-selectable for rates of
45.5 to 9600 baud.
2.
Character length, parity enable, and even/odd
parity select are jumper-selectable.
3.
Transmitted serial data is available in CTL
output jumper area.
4.
Received serial data is available in the CTL
input jumper area.
5.
Transmit ready (TRDY), receive ready (RRDY),
parity error (PE), overrun error (OE),
framing error (FE), the complements of TRDY
and RRDY, and (SIOS), which can represent
one of (OE), (PE), (FE> or the logical
O R of the three, are all available in the
CTL input jumper area.
B)
PIO
1.
Output data is latched and available at the
PIO connector.
Output Data Ready (ODR) is available at the
PIO connector.
Output Data Accepted (ODA) is available at
CTL IJA.
MIO
Specifications
The PIO input pin numbers
1 - 11
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