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The 4 output bit3 of the control port on the SIO board
are latched into the 74177 which is clocked b y a com
bination of board enable and address b it 3 and the write
strobe either from the processor or from the front panel.
The 8251 chips are selected b y address bits 1 and 2,
respectively, with address bit 0 determining whether the
chip is in control o r data mode. The read and write strobes
are supplied to complete the control, enabling the chip to
read data or write data onto the bi-directional data bus on
the board.
The four control lines desired for interrupt generation
are ORed through 7425 and the resultant value supplied
to an interrupt select jumper socket (D3) .
gate m a y be disabled b y two of the output port bits
(IEA or IEB) when interrupts are not desired.
The two megacycle system clock phase II is divided to
provide the standard baud rates for jumper selection to
channel A and B.
use of a 7493 with external gating.
rate extremely close to IS times 9600 baud.
Further division of two are made b y 7493*s to provide
most of the other standard baud rates.
standard teletype is achieved b y a divide by 11 from the
2400 baud line which is then divided b y 2 to create a
symmetrical output and supplied to the jumper socket
for 110 baud.
The phase II clock, +5 volts and ground are also supplied
to the data rate select socket for use b y the SIOC board
which connects to the SIO board through the data rate
select socket (Bll) to provide a jumper-selectable baud
rate generator for special rates.
The data and control outputs of the 8251 chips are driven
or received through 1488 or 1489 TTL to RS232 level con
verters as appropriate to the functions.
for data and control are driven through open-collector
peripheral drivers and a 220 ohm pull-up to +5 volts.
current loop input and output are driven through opto-
isolators and are designed to work adequately with either
20 or 60 miliampere current loops.
It is first divided by 13 through the
Theory of Operation
Edition 2
The 7425 OR
This produces a
110 b a u d for a
The TTL levels
The
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