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SIO THEORY OF OPERATION
To enable the SIO board, it must be properly addressed.
In the I/O port addressed.mode, address bits A4 through
A7 are jumpered to the 74LS30
The status bits SINP and SOUT are NORed, this inter
mediate value inverted, and applied (via jumper on D6)
to another of the NAND inputs.
in this mode are jumpered (via D6) to a +5 volt level.
Thus, when the selected address appears on A4-A7, and
the MPU sends a SINP or SOUT pulse, the NAND output goes
low and the board is enabled.
In the memory-mapped I/O mode, the jumpering in socket
C7 still selects an address.
interpreted in another 8 input NAND (D8), and hard-wired
to respond to the he x value FE.
should be wired to put the inverted output of D8 into
an input of C8, and the NORed output of the status bits
SINP and SOUT directly connected to the (C8) NAND's input.
The +5 volt tie line jumper in D6 should not be connected
for memory-mapped. I/O.
high and low order bits are on A4 through A 1 5 , and the
M P U does not send a SINP or SOUT pulse, the board i3
enabled.
See Diagram.
The SIO board has a bi-directional data bus on the board
which connects to the 8251 chips and to the input and
output portion of the SIO board control port.
directional bus is connected to the DATA IN and DATA OUT
busses on the IMSAI 8080 back plane through 8216 b i
directional bus driver chips.
selects these bi-directional bus driving chips and the
processor's data bus in signal (DBIN) is used to determine
the direction of driving of the bi-directional chips.
8 T 9 7 's are used to gate the control port data on the bi
directional data bus on the board.
the DBIN strobe from the processor and address bit 3.
9 - 4
Ü i c v j i y
Edition 2
(8 input NAND)
Remaining NAND inputs
See schematic.
The high-order address is
The jumper in socket D6
In.this mode, when the corrected
The board enable signal
They are enabled by
u i
o p e r a t i o n
in C 8 .
The bi
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