IMS IMSAI 8080 User Manual page 259

Pin # Name
38 /HIADD
(Cont.)
39 /RESET
40 DBIN
41
/WR
42 GROUND
43
44
45
46
47
48
49
50 GROUND
3 - 6
"A2" through "A7" are decoded.
and "A3" may be jumpered to "DON'T
CARE".
Buffered external clear signal from
microprocessor front panel switch.
Buffered "PDBIN" signal from micro­
processor.
output signal indicating to external
circuits that the data bus is in the
input mode.
Buffer /PWR" from microprocessor.
Processor command/control output used
for memory write or I/O output con­
trol.
while the "/PWR" is active.
+8V
+8V +8 volts unregulated.
+8V
+18V +18 volts unregulated.
+18V
-18V
-18 V -18 volts unregulated.
P106
Theory of Operation
TABLE 1
Processor command/control
Data on the data bus is stable
Description
"A2"