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THEORY OF OPERATION
The SIOC board is a modulo -N clock divider, where N
is user selectable.
8080 02 clock to a rate appropriate for the 8251 USART
devices.
The four 7493 counters are arranged as a 16 bit ripple
counter, clocked by the 02 clock.
and A3 are jumpered so that when the selected binary
value N (where N is selected to produce a desired final
clock rate) is reached by the counter, the counter is
reset.
The 7 430's and 7402 create the reset signal,
while the 7474 is used to gate the reset pulse and create
a symmetrical square wave output.
The final outclock frequency can be determined by:
Outclock (Hz) = 1 _
Where N is the binary value in jumpers Al and A3, and
the factor of 1/2 is the result of the final 4 2 for
the symmetrical output.
Decoupling capacitors are provided to eliminate the high
frequency noise generated by the digital currents.
2
9A
SIOC BOARD
The SIOC divides down the 2MHz
Jumper sockets, A1
.
2X10 6 Hz
2
N
SIOC Board
Rev. 2
Theory of Operation
J
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