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USER GUIDE
Board Selection
In memory read or memory write operation (as well as responding
to the output or input commands of FE) the IMSAI RAH 4A memory
board is designed to be selected as one out of a maximum poss
ible of sixteen RAM 4A memory boards present on the b u s .
achieve this one-of-sixteen selection, the top four address
lines— :A15, A14, A13 and A12 in the case of a memory read or
memory write operation (or the top four data out lines (DO 7,
DO
, DO 5 and DO 4] in the case of an output or input FE in
6
struction) — are decoded on the board via the positioning of
the jumpers installed at location C5 to give each memory board
its unique address.
route the logic
or the complements of their polarities, in such a manner that
when a board's unique address is present on the above described
lines the four inputs to the 74LS20 four input NAND gate at C4
will all be high.
This will make the output (pin
enable (BDENAJ line on the board.
desired then the jumper for that Bit should route the output of
the 74LS157 at location D5 direct to the input of the 74LS20 at
location C
, associated wi"th that Bit shall Be routed to the input
6
of the 74LS20 at location C4.
ADDRESS BIT
A15
A14
A13
16
These jumpers are implemented so as to
polarity of the above described four lines,
1
8
TABLE 1
DIP POSITION C5
Pin 9
Pin
8
Pin
Pin 7
1 0
Pin
Pin
1 1
6
Pin
Pin 5
1 2
Pin 13
Pin 4
Pin 14
Pin 3
User Guide
] go low and will assert the board
If the logic 1 polarity is
JUMPERING
Place jumper between pins 9 and
if the board is to be selected
8
when this bit is high.
Place jumper between pins 10 and
7 if the board is to be selected
when the above bit is low.
Place jumper between pins 11 and
if the board is to be selected
6
when this bit is high.
Place jumper between pins 12 and
5 if the board is to be selected
when the bit is low.
Place jumper between pins 13 and
4 if the board is to be selected
when this bit is high.
Place jumper between pins 14 and
To
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