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THEORY OF OPERATION
The PROM—4 board provides up to 4K of addressable Read
only-Memory, utilizing the Intel 8702-1702 PROM devices.
The board contains 256 bytes of memory for each 8702-1702
chip installed.
Address lines AO through A7 are run directly to all PROM
positions to select one of the 256 internal byte positions,
while address lines A
enable one particular PROM position through 8205 decoders.
Address lines A12 through A15 are jtamper-selected to de
termine the board's enabling address.
The board is enabled when the 74LS30 NAND (Cl) inputs are
all high, namely when the selected address appears on the
address bus, and the Status line SMEMR is high.
cessor Ready line is controlled by a 74195 shift register
via an 8T97.
The 74195 provides a user-selected memory
read delay, selectable with jumpers in the delay select
socket.
The 74195 shift register is reset on the rising
edge of the inverted Board Enable (BDENA) signal.
When addressed and enabled, an 8702-170Z PROM puts out its
data on the DO through D7 lines.
all PROMS are tied to these lines, and these lines are
buffered via 8T97 sections to the DIO through DI7 back
plane bus lines.
Power for the card logic is provided by a +5 volt regulator
and a -5 volt regulator-4 volt zener combination to yield
+5 and -9 volts.
tors eliminate noise from the power distribution busses. .
through All are used to select and
8
Tantalum and disc ceramic by-pass capaci
PROM-4, Rev. 3
■rneory of Operation
The Pro
The data output lines of
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