Core Registers; Table 3. Core Register Set Summary; Figure 2. Processor Core Registers - ST STM32F0 Series Programming Manual

The STM32 Cortex-M0 processor
2.1.3

Core registers

Figure 2.
/RZ UHJLVWHUV
+LJK UHJLVWHUV
3URJUDP &RXQWHU
Table 3.
Name
R0-R12
MSP
PSP
LR
PC
PSR
ASPR
IPSR
EPSR
PRIMASK
CONTROL
1. Describes access type during program execution in Thread and Handler modes. Debug access can differ.
2. Bit[24] is the T-bit and is loaded from bit[0] of the reset vector.
General-purpose registers
R0-R12 are 32-bit general-purpose registers for data operations.
12/91
Processor core registers
5
5
5
5
5
5
5
5
5
5
5
5
5
63 5
6WDFN 3RLQWHU
/5 5
/LQN 5HJLVWHU
3& 5
365
35,0$6.
&21752/
Core register set summary
(1)
Type
read-write Unknown
read-write See description
read-write Unknown
read-write Unknown
read-write See description
read-write Unknown
read-write Unknown
read-only 0x00000000
read-only Unknown
read-write 0x00000000
read-write 0x00000000
Doc ID 022979 Rev 1
*HQHUDO SXUSRVH UHJLVWHUV
363
3URJUDP 6WDWXV 5HJLVWHU
,QWHUUXSW PDVN UHJLVWHU
&RQWURO 5HJLVWHU
Reset value
General-purpose registers on page 12
Stack pointer (SP) register R13 on page 13
Stack pointer (SP) register R13 on page 13
Link register (LR) register R14 on page 13
Program counter (PC) register R15 on page 13
(2)
Program status register on page 13
Application program status register on page 14
Interrupt program status register on page 14
(2)
Execution program status register on page 15
Priority mask register on page 15
Control register on page 16
PM0215
063
6SHFLDO UHJLVWHUV
06 9
Description