Interrupt Set-Enable Register (Iser); Interrupt Clear-Enable Register (Icer) - ST STM32F0 Series Programming Manual

PM0215
4.2.2

Interrupt set-enable register (ISER)

Address offset: 0x00
Reset value: 0x0000 0000
The ISER register enables interrupts, and shows which interrupts are enabled
31 30 29 28
rs rs rs rs
15 14 13 12
rs rs rs rs
Bits 31:0 SETENA: Interrupt set-enable bits.
Write:
Read:
If a pending interrupt is enabled, the NVIC activates the interrupt based on its priority. If an
interrupt is not enabled, asserting its interrupt signal changes the interrupt state to pending,
but the NVIC never activates the interrupt, regardless of its priority.
4.2.3

Interrupt clear-enable register (ICER)

Address offset: 0x080
Reset value: 0x0000 0000
The ICER register disables interrupts, and shows which interrupts are enabled.
31 30 29 28
rc_w1 rc_w1 rc_w1 rc_w1
15 14 13 12
rc_w1 rc_w1 rc_w1 rc_w1
Bits 31:0 CLRENA: Interrupt clear-enable bits.
Write:
Read:
27 26 25
rs rs rs
11 10 9
rs rs rs
0: No effect
1: Enable interrupt
0: Interrupt disabled
1: Interrupt enabled.
27 26 25
rc_w1 rc_w1 rc_w1
11 10 9
rc_w1 rc_w1 rc_w1
0: No effect
1: Disable interrupt
0: Interrupt disabled
1: Interrupt enabled.
Doc ID 022979 Rev 1
24 23 22 21
SETENA[31:16]
rs rs rs
8 7 6
SETENA[15:0]
rs rs rs
24 23 22 21
CLRENA[31:16]
rc_w1 rc_w1 rc_w1 rc_w1
8 7 6
CLRENA[15:0]
rc_w1 rc_w1 rc_w1 rc_w1
Core peripherals
20 19 18
rs rs rs rs
5 4 3 2
rs rs rs rs
20 19 18
rc_w1 rc_w1 rc_w1
5 4 3 2
rc_w1 rc_w1 rc_w1
17 16
rs rs
1 0
rs rs
17 16
rc_w1 rc_w1
1 0
rc_w1 rc_w1
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