Application Interrupt And Reset Control Register (Aircr) - ST STM32F0 Series Programming Manual

Core peripherals
4.3.3

Application interrupt and reset control register (AIRCR)

Address offset: 0x0C
Reset value: 0xFA05 0000
The AIRCR provides endian status for data accesses and reset control of the system.
To write to this register, you must write 0x5FA to the VECTKEY field, otherwise the
processor ignores the write.
31 30 29 28
rw rw rw rw
15 14 13 12
ENDIA
NESS
r
Bits 31:16 Reserved / VECTKEY Register key
Reads as unknown
On writes, write 0x5FA to VECTKEY, otherwise the write is ignored.
Bit 15 ENDIANESS Data endianness bit
Bits 14:3 Reserved, must be kept cleared
Bit 2 SYSRESETREQ System reset request
Bit 1 VECTCLRACTIVE
Reserved for Debug use. This bit reads as 0. When writing to the register you must write 0 to
this bit, otherwise behavior is unpredictable.
Bit 0 Reserved, must be kept cleared
80/91
27 26 25
Reserved(read)/ VECTKEY[15:0](write)
rw rw rw
11 10 9
Reserved
Reads as 0.
0: Little-endian
Reads as 0.
0: No system reset request
1: Asserts a signal to the outer system that requests a reset.
Doc ID 022979 Rev 1
24 23 22 21
rw rw rw rw
8 7 6 5
20 19 18 17
rw rw rw rw
4 3 2 1
SYS VECT
RESET CLR
REQ ACTIVE
w w
PM0215
16
rw
0
Reserv
ed