Systick Control And Status Register (Stk_Csr) - ST STM32F0 Series Programming Manual

Core peripherals
4.4.1

SysTick control and status register (STK_CSR)

Address offset: 0x00
Reset value: 0x0000 0004
The SysTick CSR register enables the SysTick features.
31 30 29 28
15 14 13 12
Bits 31:17 Reserved, must be kept cleared.
Bit 16 COUNTFLAG:
Returns 1 if timer counted to 0 since last time this was read.
Bits 15:3 Reserved, must be kept cleared.
Bit 2 CLKSOURCE: Clock source selection
Selects the timer clock source.
Bit 1 TICKINT: SysTick exception request enable
Bit 0 ENABLE: Counter enable
Enables the counter. When ENABLE is set to 1, the counter starts counting down. On reaching
0, it sets the COUNTFLAG to 1 and optionally asserts the SysTick depending on the value of
TICKINT. It then loads the RELOAD value again, and begins counting.
86/91
27 26 25
11 10 9
Reserved
0: External reference clock
1: Processor clock
0: Counting down to zero does not assert the SysTick exception request
1: Counting down to zero to asserts the SysTick exception request.
0: Counter disabled
1: Counter enabled
Doc ID 022979 Rev 1
24 23 22
Reserved
8 7 6
21 20 19 18
5 4 3 2
CLKSO
URCE
rw
PM0215
17 16
COUNT
FLAG
rw
1 0
TICK EN
INT ABLE
rw rw