Behavior Of Memory Accesses; Software Ordering Of Memory Accesses; Table 11. Memory Access Behavior - ST STM32F0 Series Programming Manual

The STM32 Cortex-M0 processor
2.2.3

Behavior of memory accesses

The behavior of accesses to each region in the memory map is:
Table 11.
Address
range
0x00000000-
0x1FFFFFFF
0x20000000-
0x3FFFFFFF
0x40000000-
0x5FFFFFFF
0x60000000-
0x9FFFFFFF
0xA0000000-
0xDFFFFFFF
0xED000000-
0xED0FFFFF
0xED100000-
0xFFFFFFFF
1. See Memory regions, types and attributes on page 19
The Code, SRAM, and external RAM regions can hold programs.
2.2.4

Software ordering of memory accesses

The order of instructions in the program flow does not always guarantee the order of the
corresponding memory transactions. This is because:
●
The processor can reorder some memory accesses to improve efficiency, providing this
does not affect the behavior of the instruction sequence.
● Memory or devices in the memory map have different wait states
●
Some memory accesses are buffered or speculative.
Section 2.2.2: Memory system ordering of memory accesses on page 19
cases where the memory system guarantees the order of memory accesses. Otherwise, if
the order of memory accesses is critical, software must include memory barrier instructions
to force that ordering. The processor provides the following memory barrier instructions:
DMB The Data Memory Barrier instruction ensures that outstanding memory transactions
complete before subsequent memory transactions. See
DSB The Data Synchronization Barrier instruction ensures that outstanding memory
transactions complete before subsequent instructions execute. See
page
ISB The Instruction Synchronization Barrier ensures that the effect of all completed
memory transactions is recognizable by subsequent instructions. See
page
20/91
Memory access behavior
Memory Memory
(1)
region type
Code Normal
SRAM Normal
Peripheral Device
External
Normal
RAM
External
Device
device
Private
Strongly-
Peripheral
ordered
Bus
Device Device
63.
64.
Doc ID 022979 Rev 1
(1)
XN
Executable region for program code. Can also put
-
data here.
Executable region for data. Can also put code
-
here.
XN External device memory
- Executable region for data.
XN External device memory
This region includes the NVIC, System timer, and
XN system control block. Only word accesses can be
used in this region.
This region includes all the STM32 standard
XN
peripherals.
for more information.
PM0215
Description
describes the
DMB on page 63.
DSB on
ISB on