ST STM32F0 Series Programming Manual page 60

The STM32 Cortex-M0 instruction set
Table 22.
BL label
BX Rm
BLX Rm
Restrictions
The restrictions are:
● Do not use SP or PC in the BX or BLX instruction
●
For BX and BLX, bit[0] of Rm must be 1 for correct execution. Bit[0] is used to update
the EPSR T-bit and is discarded from the target address.
Bcond is the only conditional instruction on the Cortex-M0 processor.
Condition flags
These instructions do not change the flags.
Examples
B loopA
BL funC
BX LR
BLX R0
BEQ labelD
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Branch ranges (continued)
Instruction
; Branch to loopA
; Branch with link (Call) to function funC, return address
; stored in LR
; Return from function call
; Branch with link and exchange (Call) to a address stored
; in R0
; Conditionally branch to labelD if last flag setting
; instruction set the Z flag, else do not branch.
Doc ID 022979 Rev 1
Branch range
− 16 MB to +16 MB
Any value in register
Any value in register
PM0215