Configuration And Control Register (Ccr) - ST STM32F0 Series Programming Manual

Core peripherals
4.3.5

Configuration and control register (CCR)

Address offset: 0x14
Reset value: 0x0000 0204
The CCR is a read-only register and indicates some aspects of the behavior of the Cortex-
M0 processor.
31 30 29 28
15 14 13 12
Reserved
Bits 31:10 Reserved, must be kept cleared
Bit 9 STKALIGN
Always reads as one, indicates 8-byte stack alignment on exception entry.
On exception entry, the processor uses bit[9] of the stacked PSR to indicate the stack
alignment. On return from the exception it uses this stacked bit to restore the correct stack
alignment.
Bits 8:4 Reserved, must be kept cleared
Bit 3 UNALIGN_ TRP
Always reads as one, indicates that all unaligned accesses generate a HardFault.
Bits 2:0 Reserved, must be kept cleared
82/91
27 26 25 24
Reserved
11 10 9 8
STK
ALIGN
rw
Doc ID 022979 Rev 1
23 22 21 20
7 6 5 4
Reserved
PM0215
19 18 17
3 2 1
UN
ALIGN_
Reserved
TRP
rw
16
0