Table 8. Primask Register Bit Definitions; Table 9. Control Register Bit Definitions; Figure 5. Control Register Bit Assignments - ST STM32F0 Series Programming Manual

The STM32 Cortex-M0 processor
Table 8.
Bits
Bits 31:1
Bit 0
Control register
The CONTROL register controls the stack used when the processor is in Thread mode. See
the register summary in
Figure 5.

Table 9.
Bits
Bits 31:2
Bit 1
Bit 0
Handler mode always uses the MSP, so the processor ignores explicit writes to the active
stack pointer bit of the CONTROL register when in Handler mode. The exception entry and
return mechanisms update the CONTROL register.
In an OS environment, it is recommended that threads running in Thread mode use the
process stack and the kernel and exception handlers use the main stack. By default, Thread
mode uses the MSP. To switch the stack pointer used in Thread mode to the PSP, use the
MSR instruction to set the Active stack pointer bit to 1, see
changing the stack pointer, software must use an ISB instruction immediately after the MSR
instruction. This ensures that instructions after the ISB execute using the new stack pointer.
See ISB on page 64
16/91
PRIMASK register bit definitions
Reserved
PRIMASK:
0: No effect
1: Prevents the activation of all exceptions with configurable priority.
Table 3 on page 12
CONTROL register bit assignments
CONTROL register bit definitions
Function
Reserved
ASPSEL: Active stack pointer selection. Selects the current stack:
0: MSP is the current stack pointer
1: PSP is the current stack pointer.
In Handler mode this bit reads as zero and ignores writes.
Reserved
Doc ID 022979 Rev 1
Description
for its attributes.
5HVHUYHG
MSR on page
PM0215
  
$FWLYH VWDFN SRLQWHU
5HVHUYHG
65. When