Table 20. Adcs, Add, Rsbs, Sbcs And Sub Operand Restrictions - ST STM32F0 Series Programming Manual

The STM32 Cortex-M0 instruction set
Table 20.
Instructi
on
ADCS
ADD
ADDS
RSBS
SBCS
SUB
SUBS
Examples
Multiword arithmetic examples
Specific example: 64-bit addition
in R0 and R1 to another 64-bit integer contained in R2 and R3, and place the result in R0
and R1.
Specific example: 64-bit addition
ADDS R0, R0, R2
ADCS R1, R1, R3
Multiword values do not have to use consecutive registers.
subtraction
from another contained in R4, R5, and R6. The example stores the result in R4, R5, and R6.
Specific example: 96-bit subtraction
SUBS R4, R4, R1
SBCS R5, R5, R2
SBCS R6, R6, R3
Specific example: Arithmetic negation
complement of a single register.
Specific example: Arithmetic negation
RSBS R7, R7, #0
50/91
ADCS, ADD, RSBS, SBCS and SUB operand restrictions
Rd Rn Rm
R0-R7 R0-R7 R0-R7 -
R0-R15 R0-R15 R0-PC -
R0-R7 SP or PC -
SP SP -
R0-R7 R0-R7 -
R0-R7 R0-R7 -
R0-R7 R0-R7 R0-R7 -
R0-R7 R0-R7 -
R0-R7 R0-R7 R0-R7 -
SP SP -
R0-R7 R0-R7 -
R0-R7 R0-R7 -
R0-R7 R0-R7 R0-R7 -
; add the least significant words
; add the most significant words with carry
shows instructions that subtract a 96-bit integer contained in R1, R2, and R3
; subtract the least significant words
; subtract the middle words with carry
; subtract the most significant words with carry
; subtract R7 from zero
Doc ID 022979 Rev 1
imm
Rn
Rd and
Rn
Rd and
Rn and Rm must not both specify PC.
0-1020 Immediate value must be an integer multiple of four.
0-508 Immediate value must be an integer multiple of four.
0-7 -
Rn
0-255 Rd and
-
- -
Rn
Rd and
0-508 Immediate value must be an integer multiple of four.
0-7 -
Rn
0-255 Rd and
-
shows two instructions that add a 64-bit integer contained
shows the RSBS instruction used to perform a 1's
Restrictions
must specify the same register.
must specify the same register.
must specify the same register.
must specify the same register.
must specify the same register.
Specific example: 96-bit
PM0215