System Handler Priority Registers (Shprx); Table 31. System Fault Handler Priority Fields And Registers - ST STM32F0 Series Programming Manual

PM0215
4.3.6

System handler priority registers (SHPRx)

The SHPR2-SHPR3 registers set the priority level, 0 to 192, of the exception handlers that
have configurable priority. SHPR2-SHPR3 are word accessible. To access the system
exception priority level using CMSIS, use the following CMSIS functions (where the input
parameter IRQn is the IRQ number):
●
uint32_t NVIC_GetPriority(IRQn_Type IRQn)
●
void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
Each PRI_n field is 8 bits wide, but the processor implements only bits[7:6] of each field,
and bits[5:0] read as zero and ignore writes.
Table 31.
SVCall
PendSV
SysTick
System handler priority register 2 (SHPR2)
Address offset: 0x1C
Reset value: 0x0000 0000
31 30 29 28
rw rw rw rw
15 14 13 12
Bits 31:24 PRI_11: Priority of system handler 11, SVCall
Bits 23:0 Reserved, must be kept cleared
System handler priority register 3 (SHPR3)
Address: 0xE000 ED20
Reset value: 0x0000 0000
31 30 29 28
rw rw rw rw
15 14 13 12
Bits 31:24 PRI_15: Priority of system handler 15, SysTick exception.
This is Reserved when the SysTick timer is not implemented.
Bits 23:16 PRI_14: Priority of system handler 14, PendSV
Bits 15:0 Reserved, must be kept cleared
System fault handler priority fields and registers
Handler
PRI_11
PRI_14
PRI_15
27 26 25
PRI_11
r r r
11 10 9
27 26 25
PRI_15
r r r
11 10 9
Doc ID 022979 Rev 1
Field
System handler priority register 2 (SHPR2) on page 83
System handler priority register 3 (SHPR3) on page 83
24 23 22 21
r
8 7 6
Reserved
24 23 22 21
r rw rw rw
8 7 6
Reserved
Core peripherals
Register description
20 19 18
Reserved
5 4 3 2
20 19 18
PRI_14
rw r r
5 4 3 2
17 16
1 0
17 16
r r
1 0
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