Memory Access Instructions; Table 18. Memory Access Instructions - ST STM32F0 Series Programming Manual

PM0215
3.4

Memory access instructions

Table 18
Table 18.
Mnemonic
ADR
LDM
LDR{type}
LDR{type}
LDR
LDRD
POP
PUSH
STM
STR{type}
STR{type}
shows the memory access instructions:
Memory access instructions
Brief description
Load PC-relative address
Load multiple registers
Load register using immediate offset
Load register using register offset
Load register using PC-relative address
Load register dual
Pop registers from stack
Push registers onto stack
Store multiple registers
Store register using immediate offset
Store register using register offset
Doc ID 022979 Rev 1
The STM32 Cortex-M0 instruction set
See
ADR on page 42
LDM and STM on page 46
LDR and STR, immediate offset on page 43
LDR and STR, register offset on page 44
LDR, PC-relative on page 45
LDR and STR, immediate offset on page 43
PUSH and POP on page 47
PUSH and POP on page 47
LDM and STM on page 46
LDR and STR, immediate offset on page 43
LDR and STR, register offset on page 44
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