Table 7. Epsr Bit Definitions; Figure 4. Primask Register Bit Assignments - ST STM32F0 Series Programming Manual

PM0215
Execution program status register
The EPSR contains the Thumb state bit.
See the register summary in
assignments are:
Table 7.
Bits
Bits 31:25
Attempts to read the EPSR directly through application software using the MSR instruction
always return zero. Attempts to write the EPSR using the MSR instruction in application
software are ignored. Fault handlers can examine EPSR value in the stacked PSR to
indicate the operation that is at fault. See
page 25.
The following can clear the T bit to 0:
●
instructions BLX, BX and POP{PC}
● restoration from the stacked xPSR value on an exception return
●
bit[0] of the vector value on an exception entry.
Attempting to execute instructions when the T bit is 0 results in a HardFault or lockup. See
Lockup on page 28
Interruptable-restartable instructions
LDM and STM are interruptable-restartable instructions. If an interrupt occurs during the
execution of one of these instructions, the processor abandons execution of the instruction.
After servicing the interrupt, the processor restarts execution of the instruction from the
beginning.
Exception mask registers
The exception mask registers disable the handling of exceptions by the processor. Disable
exceptions where they might impact on timing critical tasks or code sequences.
To disable or re-enable exceptions use the MSR and MRS instructions, or the CPS
instruction to change the value of PRIMASK. See
CPSID CPSIE on page 62
Priority mask register
The PRIMASK register prevents activation of all exceptions with configurable priority. See
the register summary in
Figure 4.

Table 3 on page 12
EPSR bit definitions
Reserved.
Bit 24 T: Thumb state bit.
Bits 23:0 Reserved.
for more information.
for more information.
Table 3 on page 12
PRIMASK register bit assignments
Doc ID 022979 Rev 1
The STM32 Cortex-M0 processor
for the EPSR attributes. The bit
Description
Section 2.3.6: Exception entry and return on
MRS on page
for its attributes.
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64, MSR on page 65, and
 
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