System Level Interface; Integrated Configurable Debug; Cortex-M0 Processor Features And Benefits Summary; Cortex-M0 Core Peripherals - ST STM32F0 Series Programming Manual

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1.3.1

System level interface

The Cortex-M0 processor provides a single system-level interface using AMBA
to provide high speed, low latency memory accesses.
1.3.2

Integrated configurable debug

The Cortex-M0 processor implements a complete hardware debug solution, with extensive
hardware breakpoint and watchpoint options. This provides high system visibility of the
processor, memory and peripherals through a 2-pin Serial Wire Debug (SWD) port that is
ideal for small package devices.
1.3.3

Cortex-M0 processor features and benefits summary

● High code density with 32-bit performance
●
Tools and binary upwards compatible with Cortex-M processor family
● Integrated ultra low-power sleep modes
●
Efficient code execution permits slower processor clock or increases sleep mode time
● Single-cycle 32-bit hardware multiplier
●
Zero jitter interrupt handling
● Extensive debug capabilities
1.3.4

Cortex-M0 core peripherals

The peripherals are:
●
Nested vectored interrupt controller: The NVIC is an embedded interrupt controller that
supports low latency interrupt processing.
● System control block: The SCB is the programmers model interface to the processor. It
provides system implementation information and system control, including
configuration, control, and reporting of system exceptions.
● System timer: SysTick is a 24-bit count-down timer. Use this as a Real Time Operating
System (RTOS) tick timer or as a simple counter.
10/91 Doc ID 022979 Rev 1
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