System Control Block (Scb); Cpuid Base Register (Cpuid); Table 30. Summary Of The System Control Block Registers - ST STM32F0 Series Programming Manual

PM0215
4.3

System control block (SCB)

The System control block (SCB) provides system implementation information, and system
control. This includes configuration, control, and reporting of the system exceptions. To
improve software efficiency, the CMSIS simplifies the SCB register presentation, in the
CMSIS, the array SHP[1] corresponds to the registers SHPR2-SHPR3.
Table 30. Summary of the system control block registers
Address Name
0xE000ED00 CPUID
0xE000ED04 ICSR
0xE000ED0C AIRCR
0xE000ED10 SCR
0xE000ED14 CCR
0xE000ED1C SHPR2
0xE000ED20 SHPR3
1. See the register description for more information.
4.3.1

CPUID base register (CPUID)

Address offset: 0x00
Reset value: 0x410C C200
The CPUID register contains the processor part number, version, and implementation
information.
31 30 29 28
Implementer
r r r
15 14 13 12
r r r
Bits 31:24 Implementer: Implementer code
Bits 23:20 Variant: Variant number: The r value in the Rnpn product revision identifier
Bits 19:16 Constant: Constant that defines the architecture of the processor:
Bits 15:4 PartNo: Part number of the processor
Bits 3:0 Revision: The p value in the Rnpn product revision identifier, indicates patch release.
Type Reset value
RO 0x410CC200
(1)
RW 0x00000000
(1)
RW 0xFA050000
RW 0x00000000
RW 0x00000204
RW 0x00000000
RW 0x00000000
27 26 25
r r r r
11 10 9
PartNo
r r r r
0x41: ARM
0x0: revision 0
0xC: ARMv6-M architecture
0xC20: Cortex-M0
0x0: patch 0
Doc ID 022979 Rev 1
Section 4.3.1: CPUID base register (CPUID) on page 77
Section 4.3.2: Interrupt control and state register (ICSR) on
page 78
Section 4.3.3: Application interrupt and reset control register
(AIRCR) on page 80
Section 4.3.4: System control register (SCR) on page 81
Section 4.3.5: Configuration and control register (CCR) on
page 82
Section 4.3.6: System handler priority registers (SHPRx) on
page 83
24 23 22
Variant
r r r
8 7 6
r r r
Core peripherals
Description
21 20 19 18
Constant
r r r r
5 4 3 2
Revision
r r r r
17 16
r r
1 0
r r
77/91